Timing analysis plays an important role in the design of circuits. In the course of timing analysis, a check is made, for example, as to whether a signal is available on time and for long enough in order to be sampled in a controlled manner by a rising edge of a clock signal (so-called setup-and-hold response). Signal propagation times within a circuit can also be analyzed here.
The embedding of timing analysis into the process of development of a circuit is represented schematically in FIG. 1. The circuit is present to begin with in the form of a description at register level, e.g. in the form of RTL (register transfer level) description A. This RTL description A is converted by a synthesizer 1 into a description at gate level (gate-level description) B which, for example, may be available in VHDL (Very High Speed Integrated Circuit Hardware Description Language) or Verilog. This description B is supplied to an analysis unit 4 which carries out the timing analysis—that is to say, which analyses the timing of the circuit described by the description at gate level B. Restrictions E arising therefrom are supplied in turn to the synthesizer 1, so that the restrictions can be used for an optimization of the description at gate level B. The description at gate level B that has been optimized in this way is processed by a layout device 2, in order to obtain a layout description C. This layout description C is supplied in turn to the analysis unit 4. In particular, layout-conditioned signal propagation times or clock propagation times can be analyzed in this manner. Restrictions F arising from this, which may relate, for example, to lengths of signal paths, are supplied in turn to the layout device 2. Once the layout C has been optimized in this way, it is accepted by a unit 3 and made available for further processing in the form of description D of the circuit.
The various devices 1 to 4 here are ordinarily implemented as software in data-processing equipment. A widespread type of software for static timing analysis is, for example, the program package PrimeTime® from Synopsis®.
However, these timing analysis tools are able to process only one timing case or timing mode at a time. Real circuit designs always have various timing modes or operating modes, for example a normal operating mode and a test mode in which a circuit can be tested after production. In the test mode, phase-locked loops, for example, are bridged, and all the flip-flops or latches of the circuit are clocked with the same clock signal. In the normal operating mode, on the other hand, the clock frequencies are generally significantly higher, and various areas of the circuit are operated with various clock signals.
In the course of a process for circuit design, in general both operating modes are checked separately within the scope of the timing analysis.
Timing-analysis algorithms are also frequently integrated within the layout device 2 from FIG. 1, in order to take the timing of the circuit directly into account in the layout. Here at least, various operating modes have to be taken into account in parallel, in order not to violate timing requirements of another operating mode by an optimization of one operating mode.
Control signals ordinarily serve for changing over between the operating modes. These control signals do not change during operation of the circuit and may therefore be designated as quasi-static. These signals change over various circuit elements of the circuit between various clock modes, for example between various clock signals that are being used.
This will be elucidated on the basis of a simple circuit which is represented in FIG. 2. This circuit consists of three flip-flops 5, 6, 7 which each have a data input D, an output Q, an inverted output Q and a clock input, identified by a triangle. A data signal m is supplied to flip-flop 5. The output Q of flip-flop 5 is connected to the input D of flip-flop 6 via a path 8; the output Q of flip-flop 6 is connected to the input D of flip-flop 7 via a path 9.
Two different clock signals h and k are supplied to the circuit. By means of a change-over switch or a multiplexer 10, either the clock signal h or the clock signal k is supplied to flip-flops 5 and 6, depending on a change-over signal g. The clock signal k is always supplied to flip-flop 7. For example, k may be a clock signal that is used only in a test mode, whereas both signal h and signal k are used in normal operation of the circuit.
In this circuit, two timing paths—namely timing path 8 from flip-flop 5 to flip-flop 6 and timing path 9 from flip-flop 6 to flip-flop 7—have to be analyzed. In principle, with such a circuit it would be possible for the change-over signal g to change over from one clock-pulse period to the next. This could have the result, for example, that at the output of flip-flop 5 a signal generated with clock signal h is output which, after the change-over of the change-over signal g, is then processed further with clock signal k in flip-flop 6.
However, if the change-over signal g is a quasi-static signal which switches between various operating modes of the circuit but which is not changed itself during operation of the circuit, this case cannot occur. This case must accordingly be excluded in the course of the timing analysis, in order that no error messages are generated here or no false optimization is performed. Hitherto this has been defined by definition of so-called “false paths” between all the affected circuit elements downstream of the change-over switch 10. A typical syntax with which a program for timing analysis would be instructed to carry out the timing analysis for this circuit would look as follows:create_clock-period 22.4-waveform {0 11.2}[get_ports{CLK1}]create_clock-period 11.2-waveform {0 5.6}[get_ports{CLK2}]create_generated_clock-name “CS_high”-source[get_ports{CLK1}][get_pins {Mux1/Z}]create_generated_clock-name “CS_low”-source[get_ports{CLK2}][get_pins }Mux1/Z}]-addset_false_path-from [get_clocks{CS_high)}]to [get_clocks{CS_low}]set_false_path-from [get_clocks{CS_low)}]to [get_clocks{CS_high}]
In the first two lines, the two clock signals h, k are defined as CLK1 and CLK2 with different waveforms and clock-pulse periods. In the next two lines, two auxiliary clock signals CS_high and CS_low are defined, with which the dependence of the output of the change-over switch 10 on the change-over signal g, which does not itself appear in the description, can be established. In the last two lines, the false paths are finally defined, by virtue of which it is to be ruled out that timing paths in which, for example, flip-flop 5 is driven with clock signal h and flip-flop 6 is driven with clock signal k are considered in the timing analysis.
In the case of the relatively simple circuits represented in FIG. 2, such false paths are still relatively easy to define. However, here the change-over switch 10 and the quasi-static signal g associated with it already have to be known especially, in order to be able to define the false paths appropriately. For larger circuits—which comprise a plurality of change-over switches, several quasi-static change-over signals and a plurality of circuit elements downstream of the change-over switches—a very precise knowledge of the circuit and a great deal of time are necessary to define the false paths correctly.